Front-end Design - 芯旗电子-成为光和数据世界的探索者

Front-end design engineer (partial scheme and RTL design)

1. Be familiar with various Ethernet/SDH/OTN protocols, including IEEE 802.3 family protocols and ITU-T G.709/G.707 series protocols;

2. Be familiar with Broadcom/Barefoot/Mellanox switching chips;

3. Proficient in Verilog language, with at least 3 years of recent hands-on development experience;

4. Be proficient in VCS, ModelSim, QuestaSim and other simulation tools;

5. Have certain architecture and algorithm design capabilities, and be familiar with common SOC designs and common IP and bus specifications;

6. Demonstrate a strong sense of teamwork;

7. Be able to work effectively under pressure.

Front-end design engineer (partial synthesis and verification)

1. Proficient in Synopsys DC and PT, with more than 3 years of recent development experience;

2. Proficiency in Verilog HDL language;

3. Be familiar with SystemVerilog language;

4. Be familiar with EDA tools such as SpyGlass,nLint, and Perl/Shell/Tcl scripts;

5. Be proficient in VCS, ModelSim, QuestaSim and other simulation tools;

6. Be familiar with back-end EDA tools and back-end design processes, and be able to seamlessly communicate with back-end designers;

7. Demonstrate a strong sense of teamwork;

8. Be able to work effectively under pressure.

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