2. Be responsible for layout planning and the implementation of top-level layout stitching; 

3. Be responsible for layout-related Tape Out work including parasitic parameter extraction, timing closure, physical verification, etc.; 

4. Proficient in Synopsys/Cadence/Mentor backend EDA tools (e.g., DC/PT/FM/ICC/RedHawk/Calibre/Tessent), with at least 3 years of recent hands-on development experience;

5. Familiar with the Linux operating system; proficient in using at least one scripting language among Bash, CSH, Perl, and Tcl; 

6. Experience in layout design for 45nm and below process nodes is preferred; 

7. Demonstrate a strong sense of teamwork;

8. Be able to work effectively under pressure.